Sigma delta analog-to-digital converters (ADC's) and digital-to-analog converters (DAC's) have recently come into widespread use with the development of suitable process technology and the increase in digital audio and other applications. Sigma delta converters exhibit excellent linearity and low quantization noise. Because sigma delta ADC's utilize oversampling (sampling at rates in excess of the Nyquist rate), applications of sigma delta ADC's are typically limited to measurement, voice band and audio frequency ranges. Sigma delta ADC's and DAC's are particularly useful in mixed signal integrated circuits in which ADC, digital signal processing and DAC functions are monolithically integrated.
An important component of a sigma delta ADC is a one-bit digital-to-analog converter which receives an input from a comparator connected to the output of a loop integrator. The one-bit DAC supplies an error signal to a summing junction at the input of the sigma delta modulator loop.
Switched capacitor circuits have been used to implement the one-bit DAC in sigma delta ADC's. Typically, the basic elements of a switched capacitor circuit are a capacitor and two switches. A charge is transferred from a voltage source to the capacitor through the first switch on a first clock phase. The first switch is opened, and the charge is transferred from the capacitor to an output through the second switch on a second clock phase. The switches are typically implemented as CMOS transistors.
A first prior art sigma delta modulator circuit is shown in FIG. 3. A one-bit DAC 10 is implemented as a switched capacitor circuit. Charge is coupled from a reference voltage source VREF to capacitors 12 and 14 through switches 16, 18, 20 and 22. The charge is transferred from switches 12 and 14 to the summing junctions 23A, 23B of an integrator 24 through switches 30, 32, 34 and 36. The switches 32 and 34 are controlled by a data dependent control signal formed by logically ANDing clock phase 1 (.PHI..sub.1) with the output of comparator 38. Switches 30 and 36 are controlled by a data dependent control signal formed by logically ANDing clock phase 1 with the inverted comparator output. Charge is delivered to the summing junctions only on clock phase 1.
A second prior art circuit is shown in FIG. 4. A similar circuit is disclosed by M. Sarhang-Nejad et al in "A True 16-Bit 20 kHz Multibit Sigma Delta ADC With Digital Correction", IEEE 1992 Custom Integrated Circuits Conference Proceedings, pages 16.4.1 to 16.4.4. A one-bit DAC 40 is implemented as a switched capacitor circuit. A DAC 42 applies a data dependent reference voltage VREF to the switched capacitor circuit. The circuit of FIG. 4 does not utilize data dependent switching in the switched capacitor circuit. Charge is delivered to the summing junction only on one phase of the clock cycle. The circuit of FIG. 4 causes a nonlinear voltage dependent load on the voltage reference, which results in signal path distortion.
The prior art one-bit DAC circuits provide generally satisfactory performance. However, it is desirable to provide improved circuit structures, particularly with respect to reducing the circuit area requirements for integrated circuits.